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quad, 15 v, 256-position, digital potentiometer with pin selectable spi/i 2 c ad5263 rev. 0 in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . features 256-position, 4 - channel end-to-end r e s istance 20 k?, 50 k?, 20 0 k? pin selectable spi? or i 2 c? compatible interf ace power-on preset to midscale two package address deco de pins ad0 and a d 1 rheostat mode temperature coefficient 30 p p m/c voltage di vide r temperature coefficient 5 ppm/c wide operatin g temperature range C40c to +125 c 5 v to 1 5 v single supply; 5 v dual supply applic ati o ns mechanical pot e ntiometer replacement optical networ k adjustm e nt instrumentation: gain, offset a d justment stereo channel audio leve l control automotive e l ectronics adjustment programmable power supply programmable filters, dela ys, time constants line impedance matching low resolution dac/trimmer r e placement base station power amp biasin g sensor calibration general description the ad5263 is th e ind u s t r y s f i rs t q u ad-c hanne l , 256-p o si tion, di g i t a l p o te n t i o me te r 1 wi th a se lecta b le di gi tal in t e rfa c e . th i s d e v i ce pe rf o r m s th e sa m e e l ectr o n i c a d j u s t m e n t fun c ti o n a s m e ch a n ic a l p o ten t iom e ters o r va r i a b le r e sist o r s, wi t h en hance d r e s o l u t i o n , s o lid-s t a t e r e l i ab i l i t y , a nd s u p e r i o r lo w t e m p era t ur e co ef f i cien t p e r f o r ma n c e . e a c h c h a n ne l o f th e ad5263 o f f e rs a co m p lete l y p r og ra mma b l e val u e o f r e sis t a n ce b e tw e e n t h e a t e r m inal and t h e w i p e r , o r bet w een t h e b t e rm i n al a n d t h e w i pe r . th e f i x e d a - t o - b t e r m inal r e sis t an ce o f 20 k?, 5 0 k?, o r 200 k? has a n o minal t e m p era t ur e co ef f i cien t o f 30 p p m /c and a 1 % cha n ne l-t o - ch an nel m a tc h i ng to l e r a nc e. a n ot he r k e y fe a t u r e of t h i s p a r t is t h e ab i l i t y t o o p era t e f r o m +4.5 v t o +15 v , o r a t 5 v . w i pe r pos i ti o n p r ogr a m m i n g p r e s e t s t o m i d s c a l e u p o n po w e r - o n . o n ce po w e r e d , th e v r w i per pos i ti o n i s p r ogr a m m ed b y ei t h er t h e 3 - wire s p i o r 2- wir e i 2 c co m p a t ib le in t e r f ace . i n t h e i 2 c m o de , addi t i o n al p r og ra mma b l e log i c o u t p u t s enab le us ers to dr i v e dig i t a l l o ads, lo g i c ga tes, a n d a n a l o g sw i t ch es in t h eir sys t em s. the ad5263 is a v a i la b l e in a nar r o w bo d y t s s o p - 24. al l p a r t s a r e gua r a n t e e d to o p era t e o v er t h e a u t o m o t i v e tem p er a t ur e ra n g e o f C40c t o +125c. f o r sin g le- o r d u a l -chan n e l a p plica t ion s , r e fer t o t h e ad5260/ad52 80 o r ad5262/ad5282. func tio n a l block di agram 03142-0-001 serial input register ad5263 address decoder spi/i 2 c select logic rdac 4 register rdac 3 register rdac 1 register rdac 2 register gnd a1 w1 b1 a2 w2 b2 a3 w3 b3 a4 w4 b4 cs/ad0 sdi/sda clk/scl v l v dd v ss shdn res/ad1 dis nc/o2 sdo/o1 8 fi g u r e 1 . 1 the terms di g i tal pote n t i o me te r , vr , and rdac are use d inte rchange a bl y. purc hase of l i c e nse d i 2 c c o mp on ent s of a n al og devi c e s o r on e of i t s sub l i c ensed associated c o mpani e s conv eys a license f o r the purcha ser un d e r the philips i 2 c paten t rig h ts to use th ese co mpon en ts in an i 2 c system , provi d ed th at the system co n f o r ms to th e i 2 c stan d a r d s p ecificatio n as d e fin e d by p h ilips.
ad5263 rev. 0 | page 2 of 2 8 table of contents electrical characteristics?20 k, 50 k, 200 k versions ....... 3 timing characteristics?20 k, 50 k, 200 k versions ........... 4 absolute maximum ratings ............................................................ 5 typical performance characteristics ............................................. 6 test circuits ..................................................................................... 11 spi compatible digital interface (dis = 0) ................................ 12 i 2 c compatible digital interface (dis = 1) ................................. 13 operation ......................................................................................... 14 programming the variable resistor ......................................... 14 programming the potentiometer divider ............................... 15 pin selectable digital interface ................................................. 15 spi compatible 3-wire serial bus (dis = 0) .......................... 15 i 2 c compatible 2-wire serial bus (dis = 1) .......................... 16 additional programmable logic output ................................ 17 self-contained shutdown function ........................................ 17 multiple devices on one bus ................................................... 17 level shift for negative voltage operation ............................. 17 esd protection ........................................................................... 18 terminal voltage operating range .......................................... 18 power-up sequence ................................................................... 18 v logic power supply ................................................................... 18 layout and power supply bypassing ....................................... 18 rdac circuit simulation model ............................................. 19 applications ..................................................................................... 20 bipolar dc or ac operation from dual supplies ................. 20 gain control compensation .................................................... 20 programmable voltage reference ............................................ 20 8-bit bipolar dac ...................................................................... 21 bipolar programmable gain amplifier ................................... 21 programmable voltage source with boosted output ............ 21 programmable 4?20 ma current source ............................... 22 programmable bidirectional current source ......................... 22 programmable low-pass filter ................................................ 23 programmable oscillator .......................................................... 23 resistance scaling ...................................................................... 24 resistance tolerance, drift, and temperature coefficient mismatch considerations ......................................................... 24 pin configuration and pin function descriptions .................... 25 pin configuration ...................................................................... 25 pin function descriptions ........................................................ 25 outline dimensions ....................................................................... 26 esd caution ................................................................................ 26 ordering guide ............................................................................... 26 revision history revision 0: initial version
ad5263 rev. 0 | page 3 of 2 8 electrical characteristics?20 k, 50 k, 200 k
ad5263 rev. 0 | page 4 of 28 timing characteristic s?20 k, 50 k, 200 k + 5 v , v ss = ?5 v, v l = +5 v, v a = +v dd , v b = 0 v, ?40c < t a < +125c unless otherwise noted.) table 2. parameter symbol conditions min typ 1 max unit spi interface timing characteristics (specifications apply to all parts 6, 13 ) clock frequency f clk 25 mhz input clock pulsewidth t ch ,t cl clock level high or low 20 ns data setup time t ds 10 ns data hold time t dh 10 ns cs setup time t css 15 ns cs high pulsewidth t csw 20 ns clk fall to cs fall hold time t csh0 0 ns clk fall to cs rise hold time t csh1 0 ns cs rise to clock rise setup t cs1 10 ns reset pulsewidth t rs 5 ns i 2 c interface timing characteristics (specifications apply to all parts 6, 13 ) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for start condition t 5 0.6 s t hd;dat data hold time t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s notes 1 typicals represent average readings at 25c and v dd = +5 v, v ss = ?5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w = v dd /r for both v dd = +5 v and v ss = ?5 v. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, and w have no limit ations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 8 v l is limited to v dd or 5.5 v, whichever is less. 9 worst-case supply current consum ed when all logic-input levels set at 2.4 v, standard char acteristic of cmos logic. 10 p diss is calculated from (i dd v dd ). cmos logic level inputs resu lt in minimum power dissipation. 11 all dynamic characteristics use v dd = +5 v, v ss = ?5 v, v l = +5 v. 12 settling time depends on value of v dd , r l , and c l . 13 see timing diagrams for location of measured values. all input contr ol voltages are specified with t r = t f = 2 ns (10% to 90% of +3 v) and timed from a voltage level of 1.5 v. switching characte ristics are measured using v l = +5 v.
ad5263 rev. 0 | page 5 of 2 8 absolute maximum ratings (t a = +25c, unless otherwise noted.) table 3. parameter value v dd to gnd ?0.3 v to +16.5 v v ss to gnd 0 v to +7.5 v v dd to v ss +16.5 v v l to gnd ?0.3 v to +6.5 v v a , v b , v w to gnd v ss to v dd terminal current, ax-bx, ax-wx, bx-wx pulsed 1 20 ma continuous 3 ma digital inputs and output vo ltage to gnd 0 v to +7 v operating temperature range ?40c to +85c maximum junction temperature (t j max ) 150c storage temperature ?65c to +150c lead temperature (soldering, 10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c thermal resistance 2 ja tssop-24 143c/w 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation: (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad5263 rev. 0 | page 6 of 2 8 typical perf orm ance cha r acte ristics (r ab = 2 0 k ? un l e ss ot he r w i s e not e d. ) rhe os tat mode dnl (ls b ) code (decimal) ?1 32 0 ? 0.8 ? 0.4 ? 0.2 64 96 128 0 0.4 0.2 ? 0.6 03142-0-073 160 192 224 256 0.8 0.6 1 5v 15/0v f i gur e 2 . r - dnl vs . c o de vs . sup p l y v o lta g e rheostat mode inl (lsb) code (decimal) ?1 32 0 ? 0.8 ? 0.4 ? 0.2 64 96 128 0 0.4 0.2 ? 0.6 03142-0-002 160 192 224 256 0.8 0.6 1 5v 15/0v f i gur e 3 . r - inl vs . co de vs . sup p l y v o l t a g e rhe os tat mode dnl (ls b ) code (decimal) ?1 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 03142-0-003 160 192 224 256 0.8 0.6 1 ?40 c 25 c 85 c 125c f i gure 4. r-dnl vs. c o de; v dd = 5 v rheostat mode inl (lsb) code (decimal) ?1 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 03142-0-004 160 192 224 256 0.8 0.6 1 ?4 0 c 25c 85c 125 c f i gure 5. r-inl vs. code; v dd = 5 v p o te ntiome te r mode inl (ls b ) code (decimal) ?1 32 0 ? 0.8 ? 0.4 ? 0.2 64 96 128 0 0.4 0.2 ? 0.6 03142-0-005 160 192 224 256 0.8 0.6 1 5v 15/0v f i gur e 6 . inl vs . code vs . sup p l y v o l t age p o te ntiome te r mode dnl (ls b ) code (decimal) ?1 32 0 ? 0.8 ? 0.4 ? 0.2 64 96 128 0 0.4 0.2 ? 0.6 03142-0-006 160 192 224 256 0.8 0.6 1 5v 15/0v f i gur e 7 . dnl vs . c o de vs . sup p l y v o l t a g e
ad5263 p o te ntiome te r mode inl (ls b ) code (decimal) ?1 32 0 ? 0.8 ? 0.4 ? 0.2 64 96 128 0 0.4 0.2 ? 0.6 03142-0-007 160 192 224 256 0.8 0.6 1 ?4 0 c 25c 85c 125c f i gure 8. inl vs. code; v dd = 5 v p o te ntiome te r mode dnl (ls b ) code (decimal) ?1 32 0 ? 0.8 ? 0.4 ? 0.2 64 96 128 0 0.4 0.2 ? 0.6 03142-0-008 160 192 224 256 0.8 0.6 1 ?40 c 25c 85c 125c f i gure 9. dnl vs. c o de; v dd = 5 v fse ( l sb ) temperature ( c ) ?2.5 0 ?0.5 ?2 ?1.5 ?1 20 60 80 ?40 120 0 ?2 0 40 100 v dd /v ss = 4.5/0v v dd /v ss = 5v 03142-0-009 v dd /v ss = 16.5/0v f i gure 10. f u ll- s c al e e rror v s . t e m p er a t ur e zse ( l sb ) temperature ( c ) 0 0 1.6 0.4 0.8 1.2 20 60 80 ?40 120 2 0.2 0.6 1 1.4 1.8 ?2 0 40 100 v dd /v ss = 4.5/0v v dd /v ss = 5v 03142-0-010 v dd /v ss = 16.5/0v f i gure 11. zero -s c a le e r r o r v s . t e mpe r a t ur e i dd /i ss s u p p l y curre nt ( a) temperature ( c ) 0.001 10 0.01 0.1 1 temperature ( c ) 0 80 ?40 120 40 i dd @ v dd /v ss = 15/0v i ss @ v dd /v ss = 5v 03142-0-011 i dd @v dd /v ss = 5v v logic = 5v v ih = 5v v il = 0v f i gure 12. sup p l y current v s . t e mper at ur e s hutdown curre nt ( p a) temperature ( c ) 0.001 10 0.01 0.1 1 0 80 ?40 120 40 v dd /v ss = 15/0v v dd /v ss = 5v 03142-0-012 f i gure 13. sh u t do w n cur r ent v s . t e mper atu r e rev. 0 page 7 of 2 8
ad5263 i logic ( p a) temperature ( c ) 22 26 23 24 25 27 0 80 ?4 0 120 40 v dd /v ss = 15/0v v dd /v ss = 5v 03142-0-013 f i g u re 14. i lo g i c v s . t e mper atur e wip e r re s i s t ance ( : ) v bias (v) 45 0 75 50 60 70 51 0 ?5 1 5 85 80 65 55 r on @ v dd /v ss = 5/0v r on @ v dd /v ss = 5v 03142-0-014 r on @ v dd /v ss = 15/0v f i gure 15. wiper o n r e sistance v s . bi a s v o ltag e rheostat mode tempco (ppm/ c) code (decimal) ? 700 32 300 ? 500 ?100 100 64 96 128 0 700 500 ? 300 03142-0-015 160 192 224 256 20k : 50k : 200k : f i g u re 16. r h e o s t at m o de t e mpco ?r wb /?t v s . code p o te ntiome t e r mode te mp co (ppm/ c) code (decimal) ? 250 32 0 ? 200 ?100 ?5 0 64 96 128 0 100 50 ? 150 03142-0-016 160 192 224 256 150 20k : 50k : 200k : f i gure 1 7 . p o tentiom e ter m o de t e m p co ? r wb /? t v s . code gain ( d b) 1m ?6 0 0 100k 10k ?42 ?3 0 ?6 1k ?12 ?1 8 ?24 ?36 ?4 8 ?54 0x01 0x02 0x80 0x40 0x20 0x04 0x08 0x10 t a = 25 c v a = 50m v r m s v dd /v ss = 5 v f r eq u e n c y ( h z ) 03142-0-017 f i gure 18. g a in vs. f r equ e nc y vs. c o de ; r ab = 20 k? gain ( d b) 1m ?6 0 0 100k 10k ?42 ?3 0 ?6 1k ?12 ?1 8 ?24 ?36 ?4 8 ?54 f r eq u e n c y ( h z ) 03142-0-018 0x01 0x02 0x80 0x40 0x20 0x04 0x08 0x10 t a = 25c v a =5 0 m v r m s v dd /v ss = 5 v f i gure 19. g a in vs. f r equ e nc y vs. c o de ; r ab = 50 k? rev. 0 page 8 of 2 8
ad5263 gain ( d b) ?6 0 0 100k 10k ?4 2 ?3 0 ?6 1k ?1 2 ?1 8 ?24 ?36 ?4 8 ?54 f r e q u e ncy ( h z ) 0x01 0x02 0x80 0x40 0x20 0x04 0x08 0x10 03142-0-019 t a = 25 c v a = 50m v rm s v dd /v ss = 5 v f i gure 20. g a in vs. f r equ e nc y vs. c o de ; r ab = 20 0 k? g a in (d b ) 1m ?6 0 0 100k 10k ?42 ?3 0 ?6 1k ?12 ?1 8 ?2 4 ?3 6 ?4 8 ?5 4 frequency (hz) 03142-0-020 r = 20k : 300khz r = 200k : 35khz r = 50k : 150khz t a = 25 c v dd /v ss = 5v v a = 50mv rms f i gure 21. C3 db bandwidth psrr ( ? db) 1m 0 80 10k 1k 40 100 60 20 frequency (hz) 100k 03142-0-021 code = 0x80, v a = v dd , v b = 0v +psrr @ v dd /v ss = 5v dc 10% p-p ac ? psrr @ v dd /v ss = 5v dc 10% p-p ac fi g u r e 2 2 . p s r r v s . fr e q u e n c y v w ch 1 50.0mv m 100ns a ch2 2.70 v 1 code = 0x80 v dd /v ss = 5.5v v b /v a = 5 v 03142-0-022 f i gure 2 3 . di g i ta l f eedthro u g h v w ch 1 50.0mv t 20.00% m 2.00 p s a ch2 2.00 v 1 v dd /v ss = 5/0v v a = 5v v b = 0v 03142-0-023 t f i g u re 24. m i ds c a l e gli t ch; cod e 0x 80 C o x 7 f (4.7 nf cap a c i tor u s ed fr o m w i per to gr ou nd) v w ch 1 5.00v ch 2 5.00 v m 400ns a ch1 2.70 v 1 v dd /v ss = 5.5v v a /v b = 5 v 2 cs 03142-0-024 f i g u re 25. lar g e s i g n al s e t t l ing ti me; code 0x 0 0 C 0x ff rev. 0 page 9 of 2 8
ad5263 inl ( l sb) |v dd ? v ss | (?v) 5 ?0.5 0.5 10 15 20 0 1 0 ?1 03142-0-025 r ab = 20k : t a = 25c avg ? 3 v avg avg ? 3 v f i g u re 26. inl v s . s u p p ly v o lt ag e r-inl (ls b ) |v dd ? v ss | (v) ?2 5 1 ? 1.5 ?0.5 0.5 10 15 20 0 2 1.5 0 ?1 03142-0-026 r ab = 20k : t a = 25c avg + 3 v avg avg ? 3 v f i g u re 27. r-inl v s . sup p ly v o lt ag e rev. 0 | page 10 of 28
ad5263 test circuits f i gur e 28 t o f i gur e 38 def i n e t h e t e s t condi tions us ed in t h e p r o d uc t sp e c if ic a t io n t a b l e . 03142-0-028 v ms a w b dut v+ v + = v dd 1lsb = v + / 2 n f i gure 28. t e s t c i rc uit for p o tenti o meter d i v i de r n o nl in ea rit y e r r o r (inl, dnl) 03142-0-029 no connect i w v ms a w b dut f i gure 29. t e s t c i rc uit for r e s i s t or p o s i tion non l i n e a r i t y e rror (r heo s ta t o p er a t ion; r - inl, r - dnl) 03142-0-030 v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 ? v ms2 ]/ i w a w b dut f i gur e 3 0 . t e st c i r c ui t fo r wi p e r resi st a n c e 03142-0-031 ' v ms % dd % pss (% / %) = v+ = v dd 10% psrr (db) = 20 log ms dd ( ) v dd v a v ms a w b v+ ' v ' v ' v f i gure 31. t e st c i rc uit for p o w e r sup p l y s e nsit ivit y ( p ss, pssr) 03142-0-032 op279 w 5v b v out offset gnd offset bias a dut v in f i gure 32. t e s t c i rc uit for in ve r t ing g a in 03142-0-033 b a v in op279 w 5v v out offset gnd offset bias dut f i gure 33. t e s t c i rc uit for no ni n v er t i n g g a in 03142-0-034 +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in f i gure 34. t e s t c i rc uit for g a in v s f r eq uenc y 03142-0-035 w b v ss to v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v f i gu r e 3 5 . t e st ci r c u i t fo r i n cr em en ta l on re si sta n c e 03142-0-036 v dd v ss a w b dut gnd i cm v cm nc nc f i gure 36. t e s t c i rc uit for co m m o n m o de l e ak age cur r e n t 03142-0-037 v logic scl sca + ? i logic f i gure 37. t e s t c i rc uit for v lo g i c c u rr ent vs . di gi ta l input v o l t a g e 03142-0-038 v in n/c w1 b1 b2 w2 rdac1 a1 rdac2 v dd v ss v out cta = 20 log[v out /v in ] a2 f i gur e 3 8 . test cir c ui t fo r a n al o g c r o ssta l k rev. 0 | page 11 of 28
ad5263 rev. 0 | page 12 of 28 spi compatible digital interface (dis = 0) table 4. ad52 63 s e rial da ta-word format a d d r d a t a b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m s b l s b 2 9 2 7 2 0 03142- 0- 039 sdi clk cs v out 1 0 1 0 1 0 1 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 rdac register load f i gur e 3 9 . ad52 63 t i m i ng dia g r a m ( v a = 5 v , v b = 0 v , v w = v ou t ) 03142-0-040 t s sdi clk cs v out 1 0 1 0 1 0 v dd 0 (data in) dx dx t csho t c-sw lsb t css t cl t csh1 t cs1 t ch t ds t ch f i g u re 40. d e t a iled spi ti ming d i ag r a m ( v a = 5 v , v b = 0 v , v w = v ou t )
ad5263 rev. 0 | page 13 of 28 i 2 c compatible digital interface (dis = 1) table 5. i 2 c w r ite mod e data-word format s 0 1 0 1 1 a d 1 a d 0 w a x a 1 a 0 r s s d o 1 o 2 x a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p slave ad dress byt e instruction byte data byte table 6. i 2 c read mode data-word format s 0 1 0 1 1 a d 1 a d 0 r a d 7 d 8 d 5 d 4 d 3 d 2 d 1 d 0 a p sl ave a d dr ess byte data byte s = s t a r t co n d i t io n. p = stop c o n d i t i on . a = a c k n o w ledg e . ad 1, ad 0 = i 2 c de vic e addr ess b i ts. m u st ma tch w i t h t h e lo g i c s t a t es a t p i n s ad1, ad0. ref e r t o f i gur e 48. a1, a0 = r d a c c h a n n e l s e le c t . rs = s o f t wa r e r e set wi p e r (a1, a0) t o midsc a le p o si tio n . sd = s h u t do wn ac ti v e hig h ; ties wi p e r (a1, a0) t o t e r m inal a, o p en s t e r m inal b , rd a c r e g i st e r co n t en ts a r e no t dist urb e d . t o e x i t s h u t d o wn , t h e co m m a n d s d = 0 m u s t be ex ecu t ed f o r ea c h rd a c (a1, a0). o1, o2 = d a t a to di g i t a l output pi ns o 1 , o 2 i n i 2 c m o de , us e d t o dr i v e ext e r n al log i c. th e log i c hig h le ve l is det e r m in e d b y v l a nd t h e log i c lo w le v e l is gnd . w = w r i t e = 0. r = read = 1. d7, d6, d5, d4 , d3, d2, d1, d 0 = da t a b i ts. x = do n t c a r e . 03142-0-041 scl s d a ps p s t 8 t 9 t 9 t 8 t 3 t 2 t 1 t 4 t 7 t 5 t 10 t 2 f i g u re 41. d e t a iled i 2 c ti mi ng d i ag r a m 03142-0-042 scl frame 1 frame 2 start b y master ack by ad5263 slave address byte stop by master instruction byte sda 0 1 0 1 1 ad1 ad0 r/w xa 1 r s s d o 1 o 2 x 1 9 19 d7 d6 d5 d4 d3 d2 d1 d0 ack by ad5263 frame 3 data byte 1 9 ack by ad5263 a0 fi g u r e 4 2 . w r it ing t o the rd a c regist er 03142-0-043 no ack by master scl sda 0 1 0 1 1 ad1 ad0 r/w d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 frame 1 frame 2 s tart b y master ack by ad5263 slave address byte rdac register stop by master f i g u re 43. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de
ad5263 rev. 0 | page 14 of 28 ope ration the ad5263 is a q u ad-c ha nn e l , 256-p o si tio n , dig i tal l y co n t r o ll ed , v a ri a b l e r e s i s t o r (v r) d evi ce . t o p r og ra m t h e vr s e t t in gs, r e fer t o t h e i n t e r f ace s e c t io n s o f t h e p r e v i o u s p a g e s. the p a r t has an in t e r n al p o w e r - o n p r es et tha t places t h e wi p e r a t mids cale d u r i n g p o w e r - on, w h ich si m p lif i e s th e fa ul t co n d i tio n r e co v e r y a t po w e r - u p . i n a ddi ti o n , t h e sh u t - do wn sh dn p i n o f ad5263 p l aces t h e rd a c in an a l m o s t zer o p o w e r co n s um pt io n st a t e w h er e t e r m ina l a is op en cir c ui t e d a nd t h e wi p e r w is co n n e c t e d t o t e r m ina l b , r e su l t in g i n o n ly le aka g e c u r r en t co n s um p t io n in t h e v r s t r u c t ur e . d u r i n g s h u t - do wn, t h e vr la tch s e t t i n gs a r e ma in t a i n e d o r ne w s e t t in gs can be p r og ra mm e d . w h en the p a r t is r e t u r n e d f r o m s h u t down, t h e co r r esp o n d in g vr s e t t in g wi l l b e a p plie d t o t h e rd a c . 03142-0-044 bx wx ax sd bit d7 d6 d4 d5 d2 d3 d1 d0 rdac latch and decoder r s r s r s r s f i gur e 4 4 . ad52 63 e q ui v a le nt rd a c cir c ui t programming the variable resi stor rheostat ope r ation the n o minal r e sis t a n ce o f the rd a c be tw e e n t e r m inals a and b is a v a i la b l e in 20 k?, 50 k?, a nd 200 k?. th e f i nal tw o o r t h r e e dig i ts o f t h e p a r t n u m b er det e r m i n e t h e no minal r e sis t a n c e val u e , e . g., 20 k? = 20 ; 50 k? = 50; 20 0 k? = 200. th e nom i n a l re s i st a n c e ( r ab ) o f th e vr has 256 con t ac t p o in ts a c ce s s e d b y th e w i pe r t e rm i n al , p l us th e b t e rm in al co n t a c t . th e 8-b i t da t a i n t h e rd a c l a tch is de co de d to s e le c t o n e o f t h e 25 6 pos s i b l e set t i n gs . a s s u m i n g a 20 k ? pa r t i s u s ed , th e wi pe r ' s f i r s t co nne c t io n s t a r ts a t t h e b t e r m i n al fo r da t a 0x0 0 . sin c e t h er e is a 60 ? wi p e r con t ac t r e sis t a n ce , suc h a co nn ec tion yie l ds a minim u m o f 2 60 ? r e sis t a n c e betw een t e r m inals w and b . the s e cond co n n e c t i on is t h e f i rst t a p p o in t, and co r r esp o n d s to 198 ? (r wb = r ab /256 + r w = 7 8 ? + 2 60 ?) f o r da t a 0x01. the thir d conn e c tio n is the n e xt ta p p o in t r e p r es en tin g 216 ? (r wb = 78 ? 2 + 2 60 ?) f o r da ta 0x02, an d s o o n . e a c h ls b da ta v a l u e in cr e a s e m o v e s th e wi p e r u p t h e r e sist o r ladder un til th e l a s t ta p p o in t is r e ac h e d a t 1 9 ,982 ? (r ab C 1 ls b + 2 r w ). f i gur e 44 sh o w s a sim p lif i e d d i ag ra m o f t h e e q u i va len t rd a c cir c ui t, w h er e t h e las t r e sis t o r st r i n g wi l l n o t b e acces s e d ; t h er efo r e , t h er e is 1 ls b les s o f t h e n o minal r e sis t an ce a t f u l l scale in a d di ti o n t o th e w i p e r r e si s t a n ce . t h e g e n e ral eq ua ti o n d e t e rm in in g th e d i g i tall y p r ogra m m e d o u t p u t r e sis t an c e be tw e e n t e r m inals w and b is w ab wb r r d d r u u 2 256 ) ( ( 1 ) w h er e: d is th e decima l eq ui valen t o f th e b i na r y co de l o aded in the 8-b i t rd a c r e g i s t er . r ab is th e en d-to-end r e sis t an c e . r w is th e wi p e r r e sis t a n c e co n t r i b u t e d b y th e on r e sis t an ce o f one i n t e r n a l s w itch . i n s u mma r y , if r ab = 20 k? a n d t h e a t e r m ina l is o p en- c i r c u i t e d , th e f o ll o w i n g rd a c la t c h c o d e s r e s u l t i n th e co r r es p o n d in g o u t p u t r e sis t an c e , r wb . table 7. codes and correspo nding r wb resi stance s d (dec) r wb (?) output state 2 5 5 1 9 , 9 8 2 full-scale (r ab C 1 lsb + r w ) 1 2 8 1 0 , 1 2 0 m i d s c a l e 1 1 9 8 1 l s b 0 120 zero-scale (wiper contact resistance) n o t e tha t in t h e zer o -s cale con d i t io n a f i ni t e wi p e r r e sis t a n c e of 120 ? is p r es en t. c a r e s h o u ld be tak e n t o limi t t h e c u r r en t f l o w b e tw e e n w and b in t h is st a t e to a max i m u m p u ls e c u r r en t o f n o m o r e tha n 2 0 ma. o t her w is e , deg r ada t ion or p o s s i b le des t r u c t io n o f th e in t e r n al s w i t c h co n t ac t can o c c u r . si mi l a r to t h e me ch ani c a l p o te n t i o me te r , t h e re s i st a n c e of t h e rd a c bet w een th e wi per w a n d t e rm i n al a also p r od uces a d i g i t a l l y c o nt r o l l e d c o mp l e m e nt a r y r e s i s t a n c e , r wa . w h en t h es e t e r m ina l s a r e us e d , t h e b t e r m in a l ca n b e op e n e d . s e t t in g t h e r e sis t a n c e val u e fo r r wa st a r ts a t a max i m u m va lue o f r e sist a n ce a n d de cr e a s e s as t h e da t a lo ade d in t h e la t c h i n cr e a s e s in va l u e . the ge n e ra l e q u a t i o n fo r t h is o p era t io n is w ab wa r r d d r u u 2 256 256 ) ( (2) fo r r ab = 20 k? a n d t h e b t e r m i n al o p en-cir c u i t e d , t h e fol l o w in g r d a c la t c h co des r e su l t in t h e co r r esp o n d i n g o u t p ut re s i st anc e r wa : table 8. codes and correspo nding r wa re sistance s d (dec) r wa (?) output state 2 5 5 1 9 8 f u l l - s c a l e 1 2 8 1 0 , 1 2 0 m i d s c a l e 1 1 9 , 9 8 2 1 l s b 0 2 0 , 0 6 0 z e r o - s c a l e
ad5263 the typ i cal di s t r i b u t i on o f t h e end-t o -e n d r e si s t an ce r ab fr o m ch an nel to ch a n ne l ma tc he s w i t h i n 1 %. d e v i c e to de v i c e ma t c hin g is p r o c es s lo t dep e nden t and is p o s s ib le t o ha ve 30% va r i a t ion. si n c e t h e r e sis t an c e e l em e n t is p r o c e s s e d i n t h i n f i lm te ch nol o g y , t h e change i n r ab w i t h t e m p era t ur e has a v e r y lo w t e m p era t ur e co ef f i cien t o f 30 p p m / c. programm ing t h e po tent iomet e r divi der voltage output operation th e di g i t a l p o te n t i o me te r e a s i ly ge ne r a te s a volt age d i v i de r a t w i p e r - to - b a n d w i p e r - to - a prop or t i ona l to t h e i n put volt age f r o m t e r m inals a t o b . u n li k e t h e p o la r i ty f r o m v dd to v ss , w h i c h m u st b e p o s i t i ve, t h e volt age ac ro ss a - b , w - a , and w - b ca n be a t ei t h e r po l a ri t y , p r o v i d ed th a t v ss is p o w e r e d b y a n e g a t i ve s u p p l y . i f ig n o r i n g t h e e f fe c t o f t h e w i p e r r e sist a n ce fo r a p p r o x im a t ion, co nne c t in g t h e a t e r m ina l t o 5 v a n d t h e b ter m ina l t o g r o u nd p r o d uces a n ou t p u t v o l t a g e f r o m t h e wi p e r t o b s t a r t i n g a t 0 v u p t o 1 ls b b e l o w 5 v . e a c h ls b s t ep o f v o l t a g e is eq ual t o th e v o l t a g e a p p l ie d acr o s s t e r m inal s a - b divide d b y th e 256 p o si tio n s o f the p o t e n t iom e t e r di vider . s i n c e the ad5263 can be p o w e r e d b y d u a l s u p p lies, t h e gen e ral e q u a t i o n def i nin g t h e output vo lt ag e v w wi th r e s p ect t o gr o u n d f o r a n y v a li d i n p u t v o l t a g es a p plie d t o t e r m ina l s a a n d b is b a w v d v d d v 256 256 256 ) ( ( 3 ) f o r a m o r e acc u ra t e c a lc u l a t ion, w h ich i n cl udes t h e ef fe c t o f wi p e r r e sist an ce, v w ca n be f o u n d as b wa a wb w v d r v d r d v 256 ) ( 256 ) ( ) ( (4) sdi o p era t ion o f t h e dig i t a l p o ten t i o m e t e r in t h e divider m o de re su lt s i n a more a c c u r a te o p e r at i o n ove r te m p e r a t u r e. u n l i ke t h e rh e o s t a t m o de , t h e o u t p u t vol t a g e is de p e n d en t mainl y o n th e ra ti o o f th e in t e rn al r e s i s t a n ce s r wa and r wb , a n d n o t t h e i r a b s o l u t e v a l u es; t h er efo r e , t h e te m p er a t ur e dr if t r e d u ces t o 5 ppm / c . pin selectable digital interface the ad5263 p r o v ides the f l exi b ili t y o f a s e lec t a b le in t e r f ace . w h en t h e dig i t a l in t e r f ace s e le c t (d is) p i n is t i e d lo w , t h e sp i m o de is en ga ge d . w h en t h e d i s p i n is t i e d hi g h t o t h e v l su p p ly , t h e i 2 c m o de is en ga ge d . spi compatible 3-wire serial bus ( d is = 0) the ad5263 con t a i n s a 3 - wir e s p i co m p a t ib le dig i t a l in t e r f ace (s d i , cs , a n d c l k ) . t h e 1 0 - b i t s e r i a l w o r d m u s t b e l o a d e d w i t h a d d r e s s bit s a 1 a n d a 0 , f o l l ow e d by t h e d a t a by t e , m s b f i r s t . the fo r m a t o f t h e w o rd is sh o w n in t a b l e 4. the p o si t i ve-e d ge s e n s i t i v e cl k in p u t r e q u ir e s cle a n t r a n si t i on s t o a v o i d c l o c k i ng in co r r ec t da ta in t o t h e s e r i a l in p u t r e g i st er . st an d a rd l o g i c f a m i l i e s work we l l . i f me ch an i c a l s w i t c h e s are us ed f o r p r o d uc t eval ua tio n , t h e y s h o u ld be deb o un ce d b y a f l i p -f lo p o r o t h e r s u i t a b le m e a n s. w h e n cs is lo w , t h e clo c k lo ads da t a in t o t h e s e r i al r e g i s t er o n eac h p o si t i v e c l o c k edge (s ee f i gur e 39). table 9. ad52 63 addr es s decode table a 1 a 0 l a t c h lo a d e d 0 0 r d a c 1 0 1 r d a c 2 1 0 r d a c 3 1 1 r d a c 4 the da t a s e t u p a n d da t a h o ld t i m e s i n t h e sp e c i f ica t ion t a b l e det e r m in e t h e valid timin g r e q u ir em en ts. the ad5263 us es a 1 0 - bit s e r i a l i n p u t d a t a re g i ste r word t h a t i s t r a n s f e r re d to t h e in t e r n al r d a c r e g i s t er w h e n t h e cs line r e t u r n s to log i c hig h . n o t e t h a t onl y t h e las t 10 -b i t s t h a t a r e clo c k e d in t o t h e r e g i st er are l a tch e d i n to t h e d e c o de r . a s cs go es hig h , i t ac t i va t e s t h e addr ess de co der a n d u p d a tes t h e co r r esp o n d ing cha n n e l acco r d in g t o t a b l e 9. duri n g s h u t d o wn ( sh dn ), th e ser i al da ta o u t p u t (s d o ) p i n is fo r c e d to lo g i c hig h i n o r der to a v o i d p o w e r dissi p a t ion i n t h e ext e r n al p u l l -u p r e sis t o r . f o r a n e q ui vale n t s d o o u t p u t c i r c ui t s c h e ma tic, s e e f i gur e 45. 03142-0-045 serial register cs clk shdn res rs ck sdo d q f i gure 4 5 . d e tai l e d sdo o u tput schem a t i c o f the ad52 63 duri n g r e se t ( res ), t h e w i p e r is s e t to mids ca le. n o te t h a t unlik e sh dn , w h en t h e p a r t is t a k e n ou t o f r e s e t, t h e wi p e r wi l l r e ma in a t mi ds c a le a n d wi l l n o t r e ver t to i t s p r e - r e s e t s e t t ing. daisy-chain operation t h e ser i al da t a o u t p u t (s d o ) p i n co n t a i n s an o p en drain n-chan n e l fet . this o u t p u t r e quir es a p u l l -u p r e sist o r in o r der t o tra n sf er da t a t o th e n e xt p a c k a g e s s d i p i n. this al lo ws f o r da isy c h aining s e v e ral r d a c s f r o m a sin g le p r o c es s o r s e r i al d a t a li ne. t h e pu l l -u p r e sisto r ter m ina t ion vol t a g e can b e gr ea t e r th a n t h e v dd s u p p l y v o l t a g e . i t is r e co mm en ded t o in cr e a s e t h e clo c k p e r i o d w h en usin g a p u l l -u p r e sis t o r t o t h e s d i p i n o f t h e fol l o w in g de vic e b e c a us e ca p a c i t i v e lo adin g a t t h e da isy - ch a i n n o d e (s d o - s di) b e tw e e n d e v i ces ma y i n d u c e t i me de l a y t o s u bs e q uen t de v i ces. u s ers s h o u ld be a w a r e o f t h is p o t e n t ial p r ob le m t o achi e v e da t a t r a n sfer s u cc es sf u l l y (s e e rev. 0 | page 15 of 28
ad5263 f i gur e 46). i f tw o ad5263s a r e da isy-c h a i n e d , a t o tal o f 20 b i ts o f d a ta i s r e q u i r e d . t h e fi r s t 1 0 b i t s , c o m p l y i n g w i th th e f o rm a t s h own in t a b l e 4, g o t o u2 a n d th e s e con d 10 b i ts, wi t h t h e s a m e f o r m a t , g o t o u 1 . cs s h o u ld be k e p t lo w un ti l al l 20 b i ts a r e clo c k e d i n t o t h eir r e s p e c t i v e s e r i al r e g i s t ers. af t e r t h is, cs is pu l l e d h i g h to c o m p l e te t h e op e r a t i o n a n d l o a d t h e r d a c l a tc h . n o t e tha t da ta a p pea r s o n s d o o n th e n e ga ti v e ed g e o f th e clo c k, t h us mak i n g i t a v ai lab l e to t h e i n p u t o f t h e da i s y-cha i n e d de vice on t h e r i sin g edg e o f t h e n e xt c l o c k. 03142-0-046 ad5263 ad5263 u2 spi u1 cs sdi clk cs sdo cs clk sdi sdo clk mosi v l r p 2.2k : f i gure 46. d a isy- chain c o nfigur ation i 2 c compatible 2-wire serial bus ( d is = 1) in t h e i 2 c com p a t ib le m o de , th e rd a c s a r e conn ec ted t o th e b u s as s l a v e de v i ces. ref e r r i n g t o t a b l e 5 an d t a b l e 6, th e f i rs t b y t e o f th e ad5263 is a s l a v e addr es s b y t e , co n s is t i ng o f a 7-b i t s l a v e addr es s and a r/ w b i t. the f i v e ms bs a r e 01011 a n d t h e f o l l o w in g tw o b i ts a r e det e r m i n e d b y t h e st a t e o f t h e a d 0 an d ad1 pi n s o f t h e de vice . ad0 and a d 1 a l lo w t h e us er t o place u p t o fo ur o f t h e i 2 c co m p a t i b le de vices o n on e b u s. the 2- wir e i 2 c s e r i a l bu s proto c o l op e r a t e s a s f o l l ow s : 1. the mas t er ini t i a t e s a da t a t r a n s f er b y es t a b l is hi n g a st ar t con d i t ion, w h ich is w h e n a hi g h - t o-lo w t r a n si t i on o n the s d a lin e o c c u rs while s c l is hig h (s ee f i gur e 42). the fol l o w in g b y t e is t h e s l a v e addr es s b y t e , w h i c h co n s is ts o f t h e 7- b i t s l a ve addr es s fol l o w e d b y a n r/ w b i t. this r/ w b i t de te r m i n e s w h e t h e r d a t a w i l l b e re a d f r om or w r i tte n to t h e sla ve de v i ce . the s l a v e w h os e addr es s co r r esp o n d s t o t h e t r an smi t t e d addr es s r e s p onds b y p u l l in g t h e s d a l i n e lo w d u r i n g t h e nin t h clo c k p u ls e (t his is t e r m e d t h e ack n o w le d g e b i t). a t th i s s t a g e , all o t h e r devi ce s o n t h e b u s r e m a in idle wh ile t h e s e l e c t e d d e v i c e w a i t s for da t a to b e w r it te n to or re a d f r om i t s s e r i a l r e g i s t er . i f t h e r/ w b i t is hig h , t h e mas t er wi l l r e ad f r o m t h e sla ve de v i ce . i f t h e r/ w b i t is lo w , t h e mas t er w i l l wr i t e t o t h e s l a ve de vic e . 2. i n t h e wr i t e m o de , t h e s e con d b y t e is t h e in s t r u c t io n b y t e . the f i rst b i t (m s b ) o f t h e inst r u c t io n b y t e is a do n t c a r e . the fol l o w in g t w o b i ts, l a b e le d a1 an d a0, a r e t h e r d a c sub a d d re ss s e l e c t b i ts . the f o ur th ms b (rs) is th e mids cale r e s e t. a log i c hig h o n th i s b i t m o v e s th e wi pe r o f th e se lect e d c h a n n e l t o th e cen t er t a p w h ere r wa = r wb . this fe a t ur e ef fe c t iv e l y wr i t es o v er t h e co n t e n ts o f t h e r e g i st er , s o t h a t w h e n t a k e n o u t o f r e s e t m o de, t h e rd a c wi l l r e m a in a t mi ds ca le. the f i f t h ms b ( s d) is t h e s h ut do wn b i t. a log i c hig h c a us es th e s e le c t e d c h anne l t o o p e n circ ui t a t t e r m inal a while sh o r t i n g t h e w i p e r t o t e r m in a l b . this o p er a t ion y i e l ds a l mo st 0 ? i n r h e o st a t mo d e o r 0 v i n p o te n t i o me te r mo d e . t h i s sd b i t s e r v e s t h e s a me f u nc t i o n a s t h e sh dn pi n e x c e pt t h a t t h e sh dn p i n r e ac ts t o ac t i ve lo w . a l s o , t h e sh dn p i n a f fe c t s al l cha n n e ls, as o p p o s e d t o the s d b i t, w h ich a f fe c t s o n ly t h e chan n e l b e i n g wr i t ten t o . i t is im p o r t an t t o n o t e t h a t t h e s h u t do wn o p er a t ion do es n o t dis t ur b t h e co n t en ts o f t h e r e g i st er . w h e n b r o u g h t o u t o f sh u t dow n , t h e pr e v iou s s e t t i n g wi l l b e a p pl ie d to t h e rd a c . the n e xt tw o b i ts a r e o2 an d o 1 . the y a r e ext r a p r o g r a mma b l e lo g i c o u t p u t s t h a t can b e us e d to dr i v e o t h e r dig i t a l lo ads, log i c ga t e s, led dr i v ers, a n alog s w i t ch es, et c. the ls b is a don t ca r e (s e e t a ble 5). a f te r a c k n ow l e dg i n g t h e i n st r u c t i o n b y te, t h e l a st b y te i n w r i t e m o d e i s t h e da ta b y t e . d a ta i s tra n s m i t t e d o v e r th e s e r i al b u s in s e q u en ces o f nin e clo c k p u ls es (eig h t da ta b i ts f o l l owe d by an a c k n ow l e d g e bit ) . t h e t r ans i t i on s on t h e s d a line m u s t o c c u r d u r i n g the lo w p e r i o d o f scl an d r e ma in sta b le d u r i n g th e hig h p e r i o d o f scl (s e e f i gur e 42). 3. i n t h e r e a d m o de , th e da ta b y t e f o llo w s i m m e dia t e l y a f t e r t h e ack n o w le dg m e n t o f t h e s l a ve addr es s b y te . d a t a is t r a n smi t t e d o v er t h e s e r i al b u s in s e q u e n ces o f nin e c l o c k p u ls es (a s l ig h t dif f er en ce w i t h t h e wr i t e mo de , w h er e t h er e a r e eig h t da t a b i ts fol l o w e d b y a n ack n o w le dge b i t). s i m i la r l y , th e tra n s i ti o n s o n t h e s d a lin e m u s t occur d u ri n g th e l o w pe ri od o f s c l a n d r e m a in s t a b l e d u ri n g th e hig h p e r i o d o f scl (s ee f i gur e 43). n o t e t h a t t h e cha nne l o f in t e r e s t is t h e on e t h a t was p r e v io us l y s e le c t e d i n t h e wr i t e m o de . i n t h e cas e w h er e us ers n e e d t o r e ad t h e r d a c va l u es o f b o t h channe ls, t h e y n e e d t o p r og ra m t h e f i rs t cha n n e l in t h e wr i t e m o de and th en c h a n g e t o th e r e ad m o d e t o r e a d th e f i r s t ch a n n e l v a lu e. a f te r t h a t , t h e y ne e d to c h ange b a c k to t h e w r i t e m o d e wi t h t h e s e co nd cha n nel s e le c t e d an d r e a d t h e s e c o nd ch a n nel v a lu e i n t h e re a d mo d e ag ai n . i t i s not n e ce s s a r y fo r users t o is s u e t h e f r a m e 3 da t a b y t e in t h e wr i t e mo de fo r subs e q uen t r e a d b a ck o p er a t ion. refer to f i gur e 43 f o r th e p r ogra m m i n g f o r m a t . rev. 0 | page 16 of 28
ad5263 4. af t e r al l da ta b i ts ha v e be en r e ad o r wr i t t e n, a s t o p co ndi t ion is est a b l ish e d b y t h e mast er . a s t op co n d i t ion is def i n e d as a lo w-to -hig h t r a n s i t i o n o n t h e sd a l i ne w h i l e scl is hig h . i n wr i t e mo de , t h e mas t er wi l l p u l l t h e sd a lin e hig h d u r i n g t h e t e n t h clo c k p u ls e t o est a b l ish a st op co ndi t ion (s ee f i gur e 42). i n r e ad m o de , t h e mas t er wil l is s u e a n o ack n o w le dge fo r t h e nin t h clo c k p u ls e (i .e ., t h e s d a li ne r e ma i n s hig h ). the mas t er wi l l t h en b r in g t h e s d a li ne lo w b e fo r e t h e t e n t h cl o c k p u ls e, w h ich go es hig h t o es ta b l ish a s t o p co n d i t ion (s ee f i gur e 43). 03142-0-047 r pull-down scl o1 shdn sda ad5263 f i gure 47. sh u t do w n by inte rn al l o g i c o u tput multiple devices on one bus f i gur e 48 s h o w s f o ur ad5263 devices o n t h e s a m e s e r i al b u s. e a ch has a dif f er en t s l a v e addr e s s since t h e s t a t es o f t h eir a d 0 a n d a d 1 p i n s ar e dif f er en t. thi s al lo ws e a ch r d a c wi t h in e a ch de v i c e to b e w r it te n to or re a d f r om i n de p e nde n t l y . t h e ma ste r de vice o u t p u t b u s lin e dr i v ers ar e o p en- d ra i n pu l l -do w n s i n a full y i 2 c co m p a t i b le in t e r f ac e . a r e p e a t e d wr i t e f u n c t i on g i v e s t h e us er f l exi b i l i t y t o u p da te t h e rd a c o u t p u t a n u m b er o f tim e s a f t e r addr es sing a n d in s t r u c t in g t h e p a r t o n l y o n ce . f o r exa m ple , a f t e r t h e r d a c has ack n o w le dge d i t s sl a v e ad dr ess a n d inst r u c t io n b y tes in t h e wr i t e mo de , t h e rd a c o u t p ut w i l l u p da t e o n e a ch s u cces s i ve b y t e . i f dif f er en t in s t r u c t io n s a r e n e e d e d , t h e w r i t e/r e ad mo de has to st a r t a g ai n w i t h a ne w sla v e addr ess, inst r u c t io n, a n d da t a b y t e . s i mi la rl y , a r e p e a t e d r e ad f u n c tion o f th e rd a c is als o al lo w e d . 03142-0-048 master ad5263 sda scl r p r p +5v sda scl ad0 +5v sda scl ad5263 ad0 +5v sda scl ad5263 ad0 +5v sda scl ad5263 ad0 ad1 ad1 ad1 ad1 additi on a l programmable logic out p ut the ad5263 f e a t ur es addi t i o n a l p r og ra mma b l e log i c o u t p u t s, o1 a n d o2, w h i c h can b e us e d to dr i v e a dig i t a l lo ad , a n a l o g swi t ch es, and log i c ga t e s. o1 and o2 def a u l t t o l o g i c 0. th e v o l t a g e le ve l c a n s w in g f r o m g n d t o v l . th e logi c s t a t e s o f o1 a n d o2 c a n b e p r o g r a mm e d in f r a m e 2 u n der wr i t e mo de (s e e f i gur e 42). th es e log i c o u t p u t s ha v e ade q u a te c u r r en t dr i v ing ca p a b i li ty t o sin k /s o u r c e mi l l iam p er es o f lo ad . f i g u re 48. m u lt ip le a d 52 63 d e v i ces on o n e i 2 c b u s level shif t f o r negative voltage operat ion u s ers c a n als o ac t i va te o1 and o2 in t h r e e dif f er en t w a ys wi t h o u t a f f e c t ing th e wi p e r s e t t in gs. the y ma y do th e f o l l o w ing: the dig i t a l p o te n t iom e ter is p o p u la r in las e r di o d e dr i v er an d cer t a i n te le co m m unic a t ion e q u i pm e n t le ve l-s e t t in g a p plic a t io ns. t h ese a p p l i c a t io n s a r e so m e tim e s o p e r a t ed b e t w een gr o u n d a n d s o me nega t i v e su p p l y v o l t a g e s o t h a t t h e sys t e m s ca n be b i as e d at g r o u n d t o av o i d l a r g e b y p a s s c a p a c i t o r s t h at m a y s i g n i f i c a n t l y im p e de t h e ac p e r f o r ma n c e. l i k e m o st dig i t a l p o ten t iom e ters, th e ad5263 c a n be co nf igur e d wi t h a nega t i v e s u p p l y (s ee f i gur e 49). 1. s t ar t , sl a v e addr ess b y te, ack n o w le dge, in st r u c t io n b y te w i t h o1 a n d o2 sp e c if ie d , ack n o w le dg e , s t o p . 2. c o m p let e t h e wr i t e c y cle w i t h s t o p , t h e n st ar t , s l a v e addr ess b y te, ack n o w le dge, in st r u c t io n b y te w i t h o1 an d o2 sp e c if ie d , ack n o w le dge , st op . 3. d o n o t com p let e t h e wr i t e c y cle b y n o t is s u in g t h e st o p , t h e n st ar t , sla ve addr es s b y t e , ack n o w le dge , in s t r u c t io n b y t e w i t h o1 a n d o2 sp e c if ie d , ack n o w le dg e , s t o p . 03142-0-050 sda gnd v ss v dd scl level shifted level shifted ?5v ad5263 self-contained shutdown function sh u t down ca n b e ac t i v a te d b y st r o b i n g t h e sh dn pi n or p r o g r a mmin g t h e sd b i t i n t h e wr i t e mo de i n st r u c t io n b y te. i n a d d i ti o n , s h u t do w n ca n ev en b e i m p l em en t e d w i t h t h e de v i ce s dig i t a l o u t p u t as s h o w n in f i gure 47. i n this co nf igura t io n, the de vice wi l l b e sh u t down d u r i ng p o w e r - u p , b u t us ers a r e al lo w e d t o p r o g r a m t h e d e v i c e . t h u s , w h e n o 1 i s p r o g r a m m e d h i g h , t h e de vice wi l l ex i t f r o m t h e sh utdo w n m o de and resp on d to t h e n e w set t in g. t h is se lf- c o n ta in ed s h u t d o w n fun c ti o n allo w s a b s o l u t e sh ut do w n d u r i n g p o wer - u p , w h ich is cr ucia l in ha za r d o u s e n viro nm e n ts, w i t h ou t add i n g ext r a co m p on e n ts. f i gure 4 9 . bia s ed at nega ti v e v o l t a g e h o w e v e r , th e dig i tal in p u ts m u st als o be le ve l s h if t e d t o al lo w p r o p er o p era t ion si n c e t h e g r o u nd is n o w r e fer e n c e d t o t h e n e g a t i ve p o t e n t i a l . a s a r e s u l t , f i gur e 50 s h o w s on e im p l e m e n t a t i o n wi t h a cou p le t r a n sis t o r s an d a fe w r e sis t o r s. rev. 0 | page 17 of 28
ad5263 rev. 0 | page 18 of 28 wh e n v in is hig h , q1 is t u r n e d o n an d i t s e m i t ter is cla m p e d a t one t h re s h o l d a b ove g r ou n d . t h i s t h re sho l d a p p e ar s a t t h e b a s e o f q2, whic h c a us es q2 t o t u r n o f f . i n this s t a t e , v ou t a p p r oa c h es C 5 v . w h en v in is lo w , q1 is t u r n e d o f f a n d t h e b a s e o f q2 is p u l l ed lo w , whic h in t u r n c a us es q2 t o t u r n o n . i n this st a t e, v ou t a p p r o a c h es 0 v . b e wa r e tha t p r o p er time s h if t i n g is als o n eeded f o r s u cces s f u l co mm unic a t ion wi t h the device . 03142-0-054 a v dd b w v ss 03142-0-051 v in r3 r1 r2 10k : v out ?5 v 10k : ?5v 1k : q2 2n3906 q1 2n3906 + 5v 0v ?5v 0v f i g u re 53. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and v ss power-up sequence sin c e t h e es d pr o t e c t i o n di o d e s limi t t h e v o l t age co m p l i an ce a t t e r m inals a, b , a n d w (s ee f i gu r e 53), i t is im p o r t a n t t o p o w e r v dd and v ss bef o r e a p p l ying an y v o l t a g e t o t e r m inals a, b , and w ; o t h e r w is e , th e dio d es wil l b e f o r w a r d b i as e d s u c h tha t v dd an d v ss w i ll be po w e r e d u n in t e n t i o n a ll y a n d ma y a f f e ct th e r e s t o f t h e cir c ui t. th e i d e a l p o w e r - u p s e q u e n ce is i n t h e fol l o w in g ord e r : g n d , v dd , v ss , v l , d i gi tal i n p u ts , a n d v a/ b / w . the r e l a t i ve ord e r of p o we r i ng v a , v b , v w , a n d dig i t a l i n p u t s is n o t im p o r t an t as lon g as t h e y a r e p o w e r e d a f t e r v dd and v ss . f i gur e 5 0 . l e v e l shif t fo r bi po la r p o t e nti a l op e r a t io n esd protection a l l dig i t a l in pu t s a r e p r o t e c te d wi t h a s e r i es in pu t r e sisto r a n d p a ralle l z e n e r e s d s t r u ct ur es sh o w n in f i gur e 51 a n d f i gur e 52. this p r o t e c t i on a p plies t o d i g i t a l in p u t p i n s s d i / s d a, clk/s c l, cs /ad 0 , res /ad1, an d sh dn . v lo gi c p o wer supply the ad5263 is ca p a b l e o f o p er a t in g a t hig h v o l t a g es beyon d t h e in t e r n al log i c le v e l s, whic h a r e limi te d t o o p era t io n a t 5 v . a s a re su lt , v l a l w a y s ne e d s to b e t i e d to a s e p a r a te 2 . 7 v to 5 . 5 v s o ur ce t o en s u re p r o p er dig i tal sig n al le v e l s. l o g i c le v e l s m u s t b e li mi te d to v l , re g a rd l e ss of v dd . i n a d d i t i o n , v l sh o u ld al wa ys be les s than o r e q ual t o v dd . 03142-0-052 logic 340 : v ss layout and power supply b y passing f i g u re 51. e s d pr ot ec t i o n of d i g i t a l p i ns i t is a g o o d p r ac tice t o em p l o y co m p ac t, minim u m-lead len g th la yo u t desig n . t h e le ads t o t h e i n p u t sh o u l d b e as dir e c t as pos s i b le wi th a m i n i m u m co n d uct o r le n g th . g r o u n d p a th s s h o u ld ha v e lo w r e sis t a n ce an d l o w ind u c t an ce . 03142-0-053 a,b,w v ss s i mil a rl y , i t is al s o a g o o d p r ac tice t o b y p a s s t h e p o w e r s u p p lies wi t h q u ali t y ca p a ci t o rs f o r o p tim u m sta b ili t y . s u p p l y leads t o th e de vice s h o u l d b e b y p a s s e d wi th 0.01 f t o 0.1 f cera mic dis c o r c h i p ca p a c i t o rs. l o w es r 1 f t o 10 f ta n t a l um o r e l ec tr ol ytic ca p a ci t o rs sh o u ld als o be a p p l ied a t t h e su p p lies t o mini mi ze an y t r a n sien t dist ur b a n c e an d lo w f r e q uen c y r i p p le (s ee f i gur e 54). n o tice t h e dig i t a l g r o u n d sh o u l d als o be jo in e d r e m o te l y t o th e a n alog g r o u n d a t o n e p o in t t o minimize the gr o u n d bo un c e . f i g u re 52. e s d pr ot ec t i o n of r e s i s t o r t e r m in als terminal voltage operating ra nge the ad5263 p o si ti v e v dd a n d nega t i ve v ss po w e r s u p p l y d e f i n e s t h e b o u n da r y co n d i t io ns fo r p r o p er 3-t e r m inal dig i t a l p o t e n t iom e t e r op era t ion. s u p p ly sig n als p r es en t o n t e r m inals a, b , a n d w tha t ex ceed v dd or v ss wil l b e c l am p e d b y th e in ter n al fo r w a r d b i a s e d dio d es sh own i n f i gur e 53. 03142-0-055 gnd v ss v dd ad5263 v ss v dd c1 c2 c3 c4 10 p f 10 p f 0.1 p f 0.1 p f + + f i g u r e 5 4 . p o w e r su pp l y by pa s s i n g
ad5263 listing 1. mac r o model net list for rdac rdac circuit simulation model .param d=256, rdac=20e3 * .subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/256)*rdac+60} cw w 0 55e-12 rwb w b {d/256*rdac+60} cb b 0 25e-12 * .ends dpot the i n t e r n al p a rasi t i c c a p a ci t a nces a n d t h e ext e r n al ca p a ci t i v e lo ads do mina t e t h e ac cha r ac t e r i st ics o f t h e rd a c s. c o nf igur e d as a p o ten t iome ter divider , t h e C3 db b a ndwi d t h o f t h e ad526 3 (20 k? r e sis t o r ) m e as ur es 300 kh z a t half s c al e . f i gur e 21 p r o v ides t h e la rge sig n al b o d e plo t cha r ac t e r i s t ics o f t h e t h r e e a v a i la b l e r e sis t or v e rsio n s : 20 k?, 50 k?, a n d 2 00 k?. a p a rasi t i c s i m u l a t i on m o d e l i s s h ow n i n fi g u re 5 5 . t h e f o l l ow i n g c o d e p r o v ides a macro m o de l n e t lis t f o r th e 20 k? rd a c . 03142-0-069 20k : c a w 25pf rdac a b c b c w 25pf 55pf f i gure 55. r d a c ci rcuit s i m u l a ti on m o del f o r r d a c = 20 k rev. 0 | page 19 of 28
ad5263 rev. 0 | page 20 of 28 appli c ations bipolar dc or ac operation from dual supplies the ad5263 can b e o p er a t e d f r o m d u al s u p p lies, ena b lin g c o n t ro l of g r oun d re f e re nc e d a c s i g n a l s or bip o l a r op e r a t i o n . the ac sig n a l , as hig h as v dd /v ss , ca n b e a p plie d dir e c t ly acr o ss t e rm i n a l s a - b w i th th e o u t p u t t a k e n fr o m t e rm i n a l w . se e f i gur e 56 f o r a typ i cal cir c ui t conn ec t i o n . 03142-0-056 gnd sclk v dd ad5263 p c gnd mcsi sda scl v dd v ss 2 . 5 v p - p 5vp-p +5.0v _ 5.0v d = 0x90 a1 w1 b1 a2 w2 b2 f i g u re 56. bipol a r o p er at ion f r om d u al sup p l i es gain c o ntrol compe n sation the dig i t a l p o t e n t iom e t e r is comm on ly us e d i n ga in c o n t r o l such as t h e n o n i n v er t i n g ga i n am plif ier sh o w n in f i gur e 57. 03142-0-057 r1 25pf 47k : c1 vi b a r2 v o u1 w 200k : c2 4.7pf f i g u re 57. t y pic a l n o ni nve r t i ng g a in a m pl if ie r n o tice t h e rd a c b t e r m inal p a rasi tic c a p a ci t a nce is co nn ec t e d t o th e o p a m p n o n i n v e r ti n g n o d e . i t i n tr o d uce s a z e r o f o r th e 1/ e o t e r m wi th +20 db/dec, w h er eas a typ i cal op a m p gb p has C20 db/dec c h arac t e r i s t ics. a larg e r2 a n d f i ni te c1 can c a us e this zer o 's f r eq uen c y t o fal l w e l l be lo w t h e cr os s o v e r f r eq uen c y . th us, t h e r a te of clo s ur e b e co mes 40 db/d e c and t h e sy ste m ha s 0 o phas e ma rg in a t t h e cr os s o v e r f r e q uen c y . the o u t p ut ma y r i n g o r os ci l l a t e if t h e i n p u t is a r e c t a n gu la r p u ls e o r s t ep f u n c tion. s i mi larl y , i t is als o lik e l y t o r i n g wh en swi t c h in g b e tw e e n tw o ga i n val u es, b e c a us e t h is is e q ui val e n t t o a s t ep change a t t h e i n p u t. dep e n d in g on th e o p am p g b p , r e d u cin g t h e f e ed back r e sis t o r ma y ext e n d t h e zer o 's f r e q uen c y fa r en o u g h t o o v er co m e t h e p r ob lem. a b e t t er a p p r o a ch is to in cl ude a com p en s a t i o n ca p a c i t o r c2 t o can c e l t h e ef f e c t ca us e d b y c1. op tim u m co m p en s a t i o n o c c u rs wh en r1 c1 = r2 c2 . this is n o t a n opt i on , b e c a u s e of t h e v a r i a t i o n of r 2 . a s a re su lt , one m a y u s e t h e r e la t i on s h i p a b o v e an d s c ale c2 as if r2 is a t i t s maxi m u m va l u e. d o in g s o ma y o v er co m p e n s a te an d com p r o mis e t h e p e r f o r ma n c e s l i g h t l y w h en r2 is s e t a t lo w val u es. h o w e v e r , i t wi l l a v o i d t h e g a in p e a k i ng, r i ng in g, o r o s ci l l a t i o n in t h e w o rst cas e . f o r cr i t ica l a p plic a t io ns, c 2 sh o u ld b e fo u n d em p i r i ca l l y to su i t t h e ne e d . in ge ne r a l, c 2 i n t h e r a ng e of fe w p f to no more tha n a few t e n t hs o f pf is us ual l y adeq u a t e f o r th e co m p en s a t i o n . simi l a rl y , t h er e a r e w an d a ter m inal c a p a ci t a nces co nn e c t e d to th e o u t p u t (n o t s h o w n ) ; f o r t un a t e l y th ei r e f f e ct a t th i s n o de i s less sig n if ican t a n d t h e com p ens a t i on can b e di sr ega r de d i n mo st c a s e s . programmable voltage reference f o r v o l t a g e divi der m o de o p er a t io n (f igur e 58), i t is co mm on to b u f f er t h e o u t p u t o f t h e dig i t a l p o t e n t iom e t e r u n les s t h e lo ad is m u c h l a rg er tha n r wb . n o t onl y do es t h e b u f f er s e r v e t h e p u r p os e o f im p e dan c e con v ersio n , b u t als o al lo ws a h e a v ier lo ad to b e dr ive n . 03142-0-058 u1 vin w b a gnd v o ad8601 1 a1 +5v vout 3 +5v ad5263 ad1582 f i g u re 58. p r og r a m m ab le v o lt ag e r e f e r e nc e
ad5263 rev. 0 | page 21 of 28 simi l a r t o t h e pr e v io us exam ple, in t h e sim p ler (a nd m u ch m o re us ual) cas e w h er e k = 1, a sin g le c h a n n e l is us e d an d u1 is r e p l aced b y a ma t c h e d p a ir o f r e sis t o r s t o a p p l y v i an d C v i at t h e e n ds o f t h e dig i t a l p o t e n t iom e t e r . the r e l a t i o n s h i p b e com e s 8-bit bipol a r dac f i gur e 59 s h o w s a lo w cos t , 8-b i t, b i p o l a r d a c. i t o f f e rs th e s a me n u m b er of ad j u st a b le st ep s b u t n o t t h e p r e c isio n as c o m p are d to c o n v e n t i on a l d a c s . t h e l i ne ar it y and te m p e r a t u r e co ef f i cien t, es p e cial l y a t lo w val u es co des, a r e sk e w e d b y t h e ef fe c t s o f t h e di g i t a l p o t e n t iomet e r w i p e r r e sis t a n c e . th e o u t p ut o f t h is cir c ui t is i ( 7 ) o v d2 r1 r2 v u u u 1 256 2 1 ref o v d v u 1 256 2 ( 5 ) if r2 is la r g e , a co m p en s a t i o n c a p a ci t o r o f a f e w pf ma y b e n e ed ed t o a v o i d a n y g a i n pe a k i n g . t a b l e 10 sh o w s t h e r e s u l t o f ad j u s t in g d , wi t h a2 co nf igur e d wi t h uni t y ga in, ga in o f 2, a nd g a in o f 10. th e r e s u l t is a b i p o lar a m p l if ier wi t h lin e a r l y p r og ra mma b l e ga in an d 256-s t ep re s o lut i on . 03142-0-059 a b a1 v? v+ w u1 vin gnd v o op2177 1 vout +15v adr425 v? v+ op2177 +15v trim ?15v +5vref ?5vref a2 v i ad5263 table 10. re sult of bipolar gain a m plifie r d r1 = f , r2 = 0 r1 = r2 r2 = 9 r 1 0 C 1 C 2 C 1 0 6 4 C 0 . 5 C 1 C 5 1 2 8 0 0 0 1 9 2 0 . 5 1 5 2 5 5 0 . 9 6 8 1 . 9 3 7 9 . 6 8 0 programmable voltage source with booste d o u tput f i g u re 59. 8-bit b i pol a r da c bipolar pr ogrammable gain amplifier fo r ap p l i c at i o n s t h at r e q u i r e h i g h c u r r e n t a d j u s t m e nt , s u c h a s a las e r dio d e dr iver o r t u na b l e la s e r , a b o o s te d volt a g e s o ur ce ca n b e con s ider e d . s e e f i gur e 61. f o r a p plica t ion s r e q u ir in g b i p o l a r ga in, f i gur e 6 0 sh o w s on e i m p l em en ta ti o n s i m i la r t o t h e p r ev i o us ci r c ui t . t h e d i g i tal p o t e n t iom e t e r u1 s ets t h e ad j u s t men t ran g e . th e w i p e r v o l t a g e a t w 2 ca n th e r e f o r e be p r ogra m m e d be tw een v i a nd C k v i at a g i v e n u2 s e t t ing. c o nf igur in g a2 in t h e n o n i n v er t i n g m o de al lo ws lin e a r ga in an d a t t e n u a t io n. th e tra n sf er f u n c tio n is u u k k d2 r1 r2 v v i o 1 256 1 (6) 03142-0-061 +v w signal c c r bias ld v in a b v out u1 ad5263 u3 2n7002 ad8601 u2 ?v i l wher e k is t h e r a tio o f r wb1 /r wa 1 s et b y u1. f i g u re 61. p r og r a m m ab le bo os te r v o lt ag e s o u r c e 03142-0-060 op2177 a1 ad5263 w1 v o op2177 a2 a2 b2 v+ v _ v+ v _ v ss v dd u2 ?k v i b1 a1 c1 v i r2 r1 ad5263 u1 w2 v dd v ss i n t h is cir c ui t, t h e i n ver t in g in pu t o f t h e o p am p fo r c es t h e v ou t t o b e e q ual t o t h e wi p e r v o l t a g e s et b y t h e dig i t a l p o t e n t iom e ter . the lo ad c u r r en t is t h e n de li v e re d b y t h e s u p p ly vi a t h e n- ch an nel f e t n 1 . n 1 p o we r h a nd l i ng m u st b e a d e q u a t e to dissi p a t e p o w e r e q ua l to ( v in C v ou t ) i l . this cir c ui t can s o ur ce a maxim u m o f 100 ma wi t h a 5 v s u p p ly . f o r p r ecisio n a p plic a t ion s , a vol t a g e r e fer e n c e such as ad r42 1 , ad r03, o r ad r370 can be a p p l ie d a t the a t e r m inal o f the dig i tal p o te n t i o me te r . f i g u re 60. bipol a r pr og r a mm ab le g a i n a m pl if ie r
ad5263 rev. 0 | page 22 of 28 programmable 4C2 0 ma current source programmable bidirectional current source a p r og ra mma b l e 4C20 ma c u r r en t s o ur ce ca n b e i m ple m e n t e d wi t h t h e cir c ui t s h own in f i gur e 62. th e ref191 is a uniq ue lo w supply he a d ro o m a n d h i g h c u r r e n t h a nd l i ng pre c i s i o n re f e re n c e t h a t c a n de li v e r 20 ma a t +2.04 8 v . the lo ad c u r r en t is sim p ly t h e v o l t a g e acr o s s t e r m i n als b- w o f t h e dig i t a l p o t e n t iom e t e r divide d b y r s : f o r a p plica t ion s t h a t r e q u ir e b i d i r e c t io na l c u r r en t con t r o l o r hig h er v o l t a g e c o m p li an ce , a h o wland c u r r en t pum p can b e a s o l u t i o n (s e e f i gur e 63). i f t h e r e sis t o r s a r e ma tch e d , t h e lo ad c u r r en t is n s ref l r d v i 2 u u (8) w l r2 b v r1 r2b r2a i u ) ( ( 9 ) 03142-0-062 ? 2.048v to v l 0 to (2.048v + v l ) +5v 2 3 +5v u1 c1 4 u2 ?5v r l v l r s ref191 gnd vin vout sleep ad5263 100 : 102 : 1 p f 6 a b w op8510 v+ v? i l 03142- 0 - 0 63 op2177 v l a2 r1 r2b c1 50 : ?15v w r l +15v ?15v +15v op2177 v+ v? v+ v? a1 r2 150k : 15k : r2a 150k : r1 10pf 10pf c2 500 : 14.95k : ad5263 a ?5v +5v i l f i g u re 62. p r og r a m m ab le 4 C 2 0 ma cu rr e n t s o urc e f i g u re 63. p r og r a m m ab le bid i rec t i o n a l cur r e n t s o urc e r 2 b , i n t h eo r y , ca n be ma d e a s s m all a s n eed e d t o a c h i ev e th e c u r r en t n e e d e d wi t h in a2 s o u t p u t c u r r en t dr i v in g c a p a b i l i ty . i n this cir c ui t, o p 2177 ca n de li v e r 5 ma in ei t h er dir e c t io n, and th e v o l t a g e com p lian ce a p p r o a ch es +15 v . i t can b e sh o w n tha t t h e o u t p u t im p e dan c e is the cir c ui t is si m p le , b u t b e wa r e o f tw o t h in gs. f i rs t, d u al- s u p p ly o p a m ps a r e ide a l b e c a us e t h e g r o u n d p o t e n t ial o f t h e ref191 ca n s w in g f r o m C2.048 v a t zer o s c ale to v l a t f u l l s c ale o f t h e p o t e n t iom e t e r s e t t ing. a l t h o u g h t h e cir c ui t w o rks wi t h a sin g le s u p p ly , t h e p r og ra mma b l e r e s o l u t i o n o f t h e syst em wi l l b e re d u c e d. ) ( ) ( 2 r2b r2a 1 r 2 r r1 r2a r1 b r 1 r z o c c u u c (10) f o r a p plica t ion s t h a t deman d hi g h er c u r r en t c a p a b i li t i es, a fe w cha n g e s t o t h e c i r c ui t in f i gur e 62 wi l l p r o d uce a n ad j u s t a b le c u r r en t in t h e ra n g e o f h u n d r e ds o f ma. f i rs t, t h e v o l t a g e r e fer - en c e ne e d s t o b e r e place d wi t h a hig h c u r r en t, lo w dr o p o u t r e gu la t o r , s u c h as the ad p3333 , a n d t h e o p a m p n eeds t o b e swa p p e d wi t h a hig h c u r r en t, d u al-s u p p l y m o de l, s u c h as the ad8532. dep e ndin g on the desir e d ra n g e o f c u r r en t, a n a p p r o - p r ia te val u e fo r r s m u s t b e calc u l a t e d . b e ca us e o f th e hig h c u r r en t f l o w in g t o t h e lo ad , t h e us er m u s t p a y a t t e n t ion t o t h e lo ad im p e dan c e s o as n o t t o dr iv e t h e o p am p p a s t t h e p o si - ti v e ra il . this o u t p u t im p e dan c e ca n b e inf i ni t e if r e sisto r s r1 c and r 2 c ma t c h p r e c is e l y wi t h r1 and r2 a+r2b , r e s p e c t i v e ly . on t h e ot he r h a n d , it c a n b e ne g a t i ve i f t h e re s i stor s are not m a tc h e d. a s a r e s u l t , c1 in the ra n g e o f 1 pf t o 10 pf is n eede d t o p r ev en t oscilla t io n .
ad5263 rev. 0 | page 23 of 28 programmable low-pass f i lter programmable oscillator i n a/d con v ersio n a p p l ic a t io n s , i t is co mm on to in c l ude a n a n ti a l i a s i n g fi l t e r t o b a n d - l i m i t th e s a m p l i n g s i gn a l . d u a l - chan nel di g i t a l p o te n t i o me te rs c a n b e u s e d to c o nst r u c t a s e con d o r d er s a l l en-k ey lo w-p a s s f i l t er (s ee f i g u r e 64). th e desig n e q ua t i o n s a r e i n a clas sic w i en-b r i dg e os cil l a t o r (f igur e 65), th e w i en ne t w or k ( r , r c , c , c c ) p r o v ides p o si ti v e f e e d back, while r1 an d r 2 prov i d e ne g a t i ve f e e d b a ck . a t t h e re s o n a n t f r e q u e nc y , f o , t h e o v eral l phas e s h if t is zer o , and t h e p o si t i v e fe e d b a ck c a us es t h e cir c ui t t o os cil l a t e . 2 2 2 o o o i o s q s v v z z z ( 1 1 ) wi t h r = r c , c = c c , a n d r2 = r2a||(r2b + r di ode ), th e os ci l l a t ion f r e q uen c y is c2 c1 r2 r1 o u u u 1 z (12) r c o 1 z , o r r c f o s 2 1 ( 1 4 ) w h er e r is eq ua l t o r wa , s u c h t h a t c 2 r 2 c 1 r 1 q u u 1 1 ( 1 3 ) ab r d r 256 256 ( 1 5 ) u s ers c a n f i rs t s e le c t s o m e con v enien t val u es fo r t h e c a p a ci t o rs. t o ac hiev e maximal l y f l a t ban d wid t h w h er e q = 0.707, let c1 b e t w ice t h e si ze o f c2, a nd let r1 = r2. a s a r e s u lt , t h e us er can ad j u st r1 and r 2 to t h e s a me s e t t in gs to achi e v e t h e desir e d b a ndwi d t h . a t r e so n a n c e , set t i n g 2 r 1 r2 ( 1 6 ) b a lan c es t h e b r idg e . i n p r ac t i ce , r2 / r1 sh o u ld b e s e t s l ig h t l y g r ea t e r tha n 2 to en s u r e tha t t h e os cil l a t ion c a n s t a r t. on t h e o t h e r hand , t h e a l ter n a t i n g t u r n -o n o f t h e dio d es d1 an d d2 en s u r e s t h a t r2 / r1 is m o m e n t a r il y les s tha n 2, th er eb y st a b i l iz in g t h e o s ci l l a t ion. 03142-0-064 ad8601 v o ?2.5v r1 c1 w u1 v+ v? ab w ab r2 c c2 c rr +2.5v v i adjusted to same setting on ce t h e f r eq uen c y is s e t, t h e os cil l a t ion am p l i t ude can b e tu ne d by r2b , s i n c e d d o v r2b i v u 3 2 ( 1 7 ) f i gure 64. s a l l en- k ey l o w - p a ss f ilter v o , i d , a n d v d a r e i n te rd e p e n d e n t v a r i a b l e s . w i t h prop e r se l e cti o n o f r2 b , a n eq u i li b r i u m w i ll be r e a c h e d s u c h tha t v o co n v erg e s. r2b ca n be in s e r i es wi t h a dis c r e t e resis t o r t o in cr eas e t h e am p l i t ude , b u t t h e t o tal r e sis t an ce s h o u ld n o t b e s o la rg e t h a t i t s a t u ra t e s t h e o u t p ut . 03142-0-065 +2.5v 10k : r2a u1 ?2.5v d1 vn op1177 1k : r1 w v+ v? d2 10k : 2.1k : r2b a b w v o r' a b 2.2nf c vp 10k : w r a b 2.2nf r1 = r1' = r2b = ad5263 d1 = d2 = 1n4148 frequency adjustment amplitude adjustment f i g u re 65. p r og r a m m ab le o s ci ll at or wi t h a m pl it ude cont rol
ad5263 rev. 0 | page 24 of 28 resistance scaling resistance tolerance , drift, and temperature coeffi cient mism atch consi d era t io ns the ad5263 o f f e rs 20k?, 50k?, a nd 200k? n o minal r e sis t a n ces. u s e r s wh o n e e d a l o w e r r e sis t a n ce a nd t h e s a m e n u m b er o f s t ep ad j u s t m e n t s c a n plac e m u l t i p le de vices i n p a r a l l el. f o r e x am pl e, f i g u re 6 6 show s a s i m p l e s c he m e of u s i n g tw o c h a n ne ls in p a ral l e l . t o ad j u s t half o f th e r e sis t a n ce lin e a r ly p e r s t ep , us ers ne e d t o p r og ra m b o t h cha n n e ls to t h e s a m e se t t in g s . i n t h e rh e o s t a t m o de o p er a t io n, s u ch as t h e ga i n co n t r o l cir c ui t o f f i gur e 69, t h e t o lera n c e misma t ch b e twe e n t h e dig i t a l p o ten t iom e ter and t h e dis c r e te r e sisto r ca n c a u s e r e p e a t a b i l i t y is s u es am o n g var i o u s sys t em s. b e ca us e o f t h e i n h e r e n t ma t c hi ng o f th e s i li co n p r oce s s , i t i s p r a c t i cal t o a p p l y th e m u l t i c h a nn e l de vice in t h is ty p e o f a p pli c a t ion. a s such, r1 sh o u ld b e r e p l a c ed b y o n e o f th e c h a n n e ls o f th e d i g i tal p o t e n t i o m e t e r . r 1 s h o u ld b e p r ogra mm ed t o a s p e c i f i c v a l u e wh ile r 2 ca n b e used f o r th e ad j u s t ab l e ga in. al t h o u g h i t adds cos t , t h is a p p r o a c h mini mi zes t h e tolera n c e and t e m p er a t ur e co ef f i cien t misma t ch bet w een r 1 a n d r 2 . i n a d d i ti o n , th i s a p p r oa c h also tra c k s th e r e sis t a n c e dr if t o v er t i m e . a s a res u l t , t h es e n o n-ide a l p a ra m e ters be c o m e les s s e n s i t iv e t o sys t e m va r i a t io n s. 03142-0-066 w2 a1 b1 a2 b2 led v dd w1 03142-0-070 ad8601 v i v o a b c1 w u1 r1 r2 *replaced with another channel of rdac f i gure 66. reduc e resistanc e by h a lf wi th li ne ar a d j u stme nt char act e r i sti c s a p plica b le on ly to t h e vol t a g e divider m o d e , b y co nne c t in g a d i s c re te re s i stor i n p a r a l l el a s s h ow n i n f i g u re 6 7 , a prop or t i on a t ely l o we r vo lt age app e ar s at t e r m i n a l a . t h i s t r a n s l a t es i n t o a f i n e r deg r e e o f p r e c isio n b e c a us e t h e s t ep si ze a t t e r m inal w wil l be smal ler . the v o l t a g e can b e f o un d as r1 r r1 r r2 v d d v ab ab dd w || || 256 ) ( u u (18) f i gure 69. lin e ar g a in c o nt r o l w i th t r ack i ng resistance t o ler a nc e and d r if t 03142-0-067 w a b r1 r2 r1 << r ab v dd n o ti ce tha t t h e ci r c ui t i n f i gur e 70 ca n also be used t o tra c k t h e t o lera n c e , tem p era t ur e co ef f i cie n t, an d dr if t i n t h is p a r t ic u l a r a p p l i c a t i o n . h o w e v e r , th e c h a r act e ri s t i c s o f th e tra n s f e r fun c ti o n c h a n g e f r o m a lin e a r t o a ps eudo-loga r i t hmic ga in f u n c tion. 03142-0-071 ad8601 v i v o a r b c1 w u1 f i gu r e 6 7 . d e cr ea sin g s t e p siz e b y l o w e r i ng the nominal resistan c e f i g u re 6 6 an d fi g u re 6 7 show appl i c a t i o ns i n w h i c h t h e d i g i t a l p o te n t i o me te rs change s t e p s l i ne arly . o n t h e ot he r ha nd, l o g t a p e r a d j u st m e n t is usua l l y p r efer r e d in a p plic a t i o n s such as vo lu me c o n t ro l. f i g u re 6 8 show s anot he r me t h o d of re s i st an c e s c a l in g w h ich pr o d uces a ps eud o -log t a p e r o u t p u t . i n t h is ci r c ui t , th e s m alle r th e v a l u e o f r 2 wi th r e s p ect t o r ab , t h e m o r e t h e o u t p ut a p p r o a ch es log typ e b e ha vio r . f i gure 70. no nl ine a r g a i n co ntrol wit h t r a c k i ng resi sta n c e t o ler a nc e and dr i f t 03142-0-068 v i v o a b r1 r2 f i gur e 6 8 . resi st or sc ali n g wi th l o g a d justm e nt cha r a c ter i stics
ad5263 rev. 0 | page 25 of 28 pin conf iguration and pi n function descriptions pin c o nfig uratio n 03142-0-072 b1 1 a1 2 w1 3 b3 4 a3 5 b2 a2 w2 b4 a4 24 23 22 21 20 6 7 8 9 10 19 18 17 16 15 11 12 14 13 w3 v dd gnd dis v logic w4 v ss nc/o2 sdo/o1 shdn sdi/sda clk/scl res/ad1 cs/ad0 ad5263 tssop-24 top view (not to scale) f i g u re 71. 24-l e ad t sso p pin func ti on descrip t io ns table 11. p i n n a m e d e s c r i p t i o n 1 b1 resistor termin al b1 2 a1 resistor terminal a1 (addr = 0 0 ) 3 w 1 wiper terminal w1 4 b3 resistor termin al b3 5 a3 resistor terminal a3 6 w3 wiper terminal w3 (addr = 10) 7 v dd positive power s u pply, specified for +5 v to +15 v operation. 8 g n d g r o u n d 9 dis digital interface select (spi/i 2 c select) . spi when dis = 0, i 2 c when dis = 1 1 0 v logic 2.7 v to 5.5 v lo gic supply voltage. the logic supply voltage sh ould always be l e ss than or e q ual to v dd . in addi tion, logic levels must be li mited to the lo gic supply vo ltage regardless of v dd . 11 sdi/sda sdi = 3-wire serial data input. sda = 2-wire serial data input/ output. 12 clk/scl serial clock input 13 cs /ad0 chip sel e ct in spi mode. device addres s bit 0 in i 2 c mode. 14 res /ad1 reset in s p i mo de. device addr es s bit 1 in i 2 c mode. 15 shdn shutdown. shorts wiper to terminal b, opens terminal a. tie to +5 v supply if not used. do not tie to v dd if v dd > 5 v. 16 sdo/o1 serial data output in spi mode, open- d r ain tran sistor require s p u ll-up resistor. digital output o1 in i 2 c mode, can be us ed to drive external lo gic. 17 nc/o2 no connection i n spi mode. digi tal output o2 in i 2 c mode, can be used to drive external logic. 18 v ss negative power supply, specifie d fo r operation from 0 v to C5 v. 19 w4 wiper terminal w4 (addr = 11) 20 a4 resistor terminal a4 21 b4 resistor termin al b4 22 w2 wiper terminal w2 (addr = 01) 23 a2 resistor terminal a2 24 b2 resistor termin al b2
ad5263 rev. 0 | page 26 of 28 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane compliant to jedec standards ms-153ad 0.10 coplanarity f i g u re 72. 24-l e ad thin shr i nk s m al l o u t line p a ckag e [ t ssop ] (ru - 24) di me nsio ns sho w n i n mi ll im e t e r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. orderi ng guide tab l e 12. ord e ri ng gui d e model 1 r ab ( k ? ) t e m p e r a t u r e package descri p t i o n package option parts per cont ainer AD5263BRU20 20 C40c to +125c tssop-24 ru-24 62 AD5263BRU20- reel7 20 C40c to +125c tssop-24 ru-24 1,000 ad5263bru50 50 C40c to +125c tssop-24 ru-24 62 ad5263bru50- reel7 50 C40c to +125c tssop-24 ru-24 1,000 AD5263BRU200 200 C40c to +125c tssop-24 ru-24 62 AD5263BRU200 -reel7 200 C40c to +125c tssop-24 ru-24 1,000 ad5263eval see note 2 evaluation boar d 1 p a ck age brand i ng: line 1 co ntains the mo de l numbe r, line 2 co ntains the e n d -to -e nd res i s t ance , and line 3 co ntain s the d a te cod e yy ww. 2 th e evaluat i on board is s h ippe d with the 20 k ? r ab re si st or opt i on ; h o w e ver, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le r e si st or va lu e opt i on s. the ad5263 con t a i n s 5,184 tran sis t o r s. die size: 108 mil 198 mil = 21,384 s q . mil .
ad5263 rev. 0 | page 27 of 28 notes
ad5263 rev. 0 | page 28 of 28 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d emar ks are the proper ty o f th eir respectiv e c o mpan ies . c03142-0-6/03(0)

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